Hardware

Latest Top500 list, looking beyond the number 1

Author: Adrian Jackson
Posted: 21 Jun 2016 | 17:13

There's been a lot of discussion about the latest Top500 list, released this week at ISC16.  Most of the interest has been in the whopping new Chinese system, Sunway TaihuLight, which has come in at number 1 on the list with a massive 93 PFlop/s rpeak Linpack performance, and 125 PFlop/s rmax theoretical peak performance (3 times bigger than the previous number 1 system).Top500

Whilst this is a very interesting system, and much bigger than is currently planned elsewhere, it's not unknown for very large systems to come in and dominate the list like this.  Back in 2002, the Japanese Earth Simulator system became the number 1 machine with an rpeak of ~5x that of the previous number 1 system, and it stayed as the top machine for a number of years.

Investigating power use in parallel computing

Author: Mirren White
Posted: 3 Jun 2016 | 16:09

The Adept project has been working hard for over two years to further understanding of how power is used in parallel software and hardware, and we are now on the finishing straight. 

It's a good time to take stock of our achievements and reflect on how to focus our efforts in the final phase. Also to consider life after the project ends: how do we want to exploit the technologies we have developed and the knowledge we have gained? How do we ensure a lasting legacy for Adept?

HPC hardware in 2016 and beyond

Author: Adrian Jackson
Posted: 19 Apr 2016 | 23:14

Anyone taking more than a passing interest in HPC hardware recently will have noticed that there are a number of reasonably significant trends coming to fruition in 2016. Of particular interest to me are on-package memory, integrated functionality, and new processor competitors.  Intel Xeon Phi (KNL) Die

On-package memory, memory that is directly attached to the processor, has been promised for a number of years now. The first product of this type I can remember was Micron's Hybrid Memory Cube around 2010/2011, but it's taken a few years for the hardware to become mature enough (or technically feasible and cheap enough) to make it to mass market chips. We now have it in the form of MCDRAM for Intel's upcoming Xeon Phi processor (Knights Landing), and as HBM2 on Nvidia's recently announced P100 GPU.

What's inside the box? Building computers from scratch

Author: Iain Bethune
Posted: 28 Sep 2015 | 13:28

Last weekend, a team of us attended Bang Goes The Borders, a regional science festival hosted by St Mary's school in Melrose.

This was the fourth year we've been there, and as usual there were around 1000 school kids and their families keen to get their hands on all kinds of science- and technology-based activities.

Although our "dinoracer" has been a big favourite for the last few years, this time we took along two completely new activities: the Supercomputing App and the Build-a-PC Junkyard Challenge - which I'd like to tell you about...

War in the coding world

Author: Adrian Jackson
Posted: 11 Sep 2015 | 13:41

It's not often that the internecine rivalries of the HPC research and development community spill over into the public arena. However, a video recently posted on YouTube (and the associated comments), ostensibly a light-hearted advert for a SC15 tutorial on heterogenous programming, shows how real and deep these rivalries can be.

HPCG: benchmarking supercomputers

Author: Adrian Jackson
Posted: 30 Jul 2015 | 14:40

HPCG

The LINPACK library (often known as HPL) has been used to benchmark large-scale computers for over 20 years, with the results being published in the Top500 list. But does it accurately reflect the performance of real applications?

ParCo Symposium on Xeon Phi experiences

Author: Adrian Jackson
Posted: 20 Jul 2015 | 17:12

ParCo Symposium

Experiences of porting and optimising code for Xeon Phi processors

EPCC is jointly organising a symposium at the ParCo conference on experiences from those working on porting and optimising codes for this architecture about the challenges and successes they have experienced when working with the Xeon Phi, and how these also apply to standard parallel computing hardware.

Next Generation Computational Modelling Summer School

Author: Adrian Jackson
Posted: 15 Jul 2015 | 15:06

Discussions on computing

Myself and Fiona ReidNGCM - Next Generation Computational Modelling recently presented a 2-day course on porting and optimising for the Xeon Phi at the NGCM (Next Generation Computational Modelling) summer academy in Southampton. 

This one-week academy is designed to give PhD students some of the skills they need to undertake the range of computational simulations and data analysis tasks that their work requires.

Day 5 - Wrapping up the week

Author: Adrian Jackson
Posted: 21 Jun 2015 | 20:02

The final analysis and future plans

A week ago we finished our 5 days of intensive work optimising CP2K (and to a lesser extent GS2) for Xeon Phi processors. As discussed in previous blog posts (Day4, Day3, Day2, Day1), this was done in conjunction with research engineers from Colfax, and built on the previous year's work on these codes by EPCC staff through the Intel-funded IPCC project.

Day 4 of IPCC-Colfax work at EPCC

Author: Adrian Jackson
Posted: 12 Jun 2015 | 15:41

MPI and vectorisation: Two ends of the optimisation spectrum

Day four of this week of intensive work optimising codes for Xeon Phi saw a range of work. The majority of the effort focussed on the vectorisation performance of CP2K and GS2; looking at the low level details of the computationally-intensive parts of these codes and seeing whether the compiler is producing vectorised codes, and if not is there anything that can be done to make the code vectorise.

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