Hardware

ARCHER: the mum spin

Author: Lorna Smith
Posted: 25 Apr 2014 | 08:51

How does the national supercomputing service compare with two boys aged 5 and 6?

Lorna Smith (ARCHER Computational Science & Engineering Deputy Director) gave the answers during her talk at the Women in HPC launch.

MIC check

Author: Iain Bethune
Posted: 12 Jun 2013 | 13:20

Following on from my recent post on Xeon Phi, thanks to the hard work of our Systems Development Team we now have a fully configured server sporting the two Intel 5110P Many Integrated Core (MIC) co-processor cards installed and ready to go. The imaginately named 'phi' machine is connected to our internal Hydra cluster and is available for staff, students and visitors to port and test their applications.

From multi to many cores: Intel Xeon Phi at EPCC

Author: Iain Bethune
Posted: 12 Apr 2013 | 14:30

Two shiny new Intel Xeon Phi 5110P co-processors have recently arrived at EPCC.

Based on Intel's Many Integrated Core (MIC) architecture, each card comprises 60 cores with 4-way SMT and a 512 bit wide SIMD vector unit.  At a clock speed of 1.053 GHz, this gives an aggregate peak double precision floating point performance of 1.01 TFLOP/s - all in a PCI card package, and using less than 225 Watts of power.  

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