Hardware

Last week saw EPSRC host a user meeting to discuss the phase 2 upgrade of ARCHER, the UK's national supercomputing service.

This post was written by TeamEPCC, four MSc in HPC students who achieved the highest-ever LINPACK score in the Student Cluster Competition at ISC14. 

In the photo (left to right): Chenhui Quan, Konstantinos Mouzakitis, Emmanouil Farsarakis (Manos) and Georgios Iniatis. 

EPCC will be exhibiting in Booth 920.

International Supercomputing Conference (ISC) is one of the main events in the field of high performance computing, networking and storage. It has a diverse programme of keynote talks, research presentations, tutorials, BoFs and satellite events provided by 300 expert speakers along with over 170 exhibitors and 3,000 attendees. As usual, there will be a significant EPCC representation.

We have recently agreed a new collaboration with Intel.

How does the national supercomputing service compare with two boys aged 5 and 6?

Lorna Smith (ARCHER Computational Science & Engineering Deputy Director) gave the answers during her talk at the Women in HPC launch.

Following on from my recent post on Xeon Phi, thanks to the hard work of our Systems Development Team we now have a fully configured server sporting the two Intel 5110P Many Integrated Core (MIC) co-processor cards installed and ready to go. The imaginately named 'phi' machine is connected to our internal Hydra cluster and is available for staff, students and visitors to port and test their applications.

Two shiny new Intel Xeon Phi 5110P co-processors have recently arrived at EPCC.

Based on Intel's Many Integrated Core (MIC) architecture, each card comprises 60 cores with 4-way SMT and a 512 bit wide SIMD vector unit.  At a clock speed of 1.053 GHz, this gives an aggregate peak double precision floating point performance of 1.01 TFLOP/s - all in a PCI card package, and using less than 225 Watts of power.