Posted: 21 Jun 2016 | 17:13
There's been a lot of discussion about the latest Top500 list, released this week at ISC16. Most of the interest has been in the whopping new Chinese system, Sunway TaihuLight, which has come in at number 1 on the list with a massive 93 PFlop/s rpeak Linpack performance, and 125 PFlop/s rmax theoretical peak performance (3 times bigger than the previous number 1 system).
Whilst this is a very interesting system, and much bigger than is currently planned elsewhere, it's not unknown for very large systems to come in and dominate the list like this. Back in 2002, the Japanese Earth Simulator system became the number 1 machine with an rpeak of ~5x that of the previous number 1 system, and it stayed as the top machine for a number of years.
Posted: 26 Apr 2016 | 13:07
I had a recent query from some users with a problem with the default version of the Intel Fortran compiler on ARCHER (v188.8.131.52). It was a nice query to get because the users had done all the work already; they'd identified the problem, found a test code that demonstrated it, and told me what the solution would be for them.
Fortunately, the solution was easy, this bug has been fixed in a newer version of the compiler (184.108.40.206), which is installed and available on ARCHER, but just isn't the default (we tend to keep the default version slightly behind the latest release but as new as possible), so they simply have to swap the compiler modules then their code can compile and run correctly.
Posted: 15 Feb 2016 | 15:38
In early December we added a visualisation of the most heavily used application codes to the ARCHER website. At the moment it only shows data for the current month, but we've been recording the data since the ARCHER service began back in 2013 (table below).
Posted: 11 Sep 2015 | 13:41
It's not often that the internecine rivalries of the HPC research and development community spill over into the public arena. However, a video recently posted on YouTube (and the associated comments), ostensibly a light-hearted advert for a SC15 tutorial on heterogenous programming, shows how real and deep these rivalries can be.
Posted: 30 Jul 2015 | 14:40
Posted: 20 Jul 2015 | 17:12
Experiences of porting and optimising code for Xeon Phi processors
EPCC is jointly organising a symposium at the ParCo conference on experiences from those working on porting and optimising codes for this architecture about the challenges and successes they have experienced when working with the Xeon Phi, and how these also apply to standard parallel computing hardware.
Posted: 3 Apr 2015 | 14:30
EPCC will be exhibiting at this year’s Supercomputing in Engineering Show at the Derby Roundhouse on the 15th and 16th April. The show is run in parallel with the Engineering Simulation Show and attendance is free, so this is an ideal opportunity for you to come and talk to us about how we can help transform your simulation and modeling activities using High Performance Computing.
Posted: 19 Jan 2015 | 11:03
Transformer park, Advanced Computing Facility Plant Room C.
The media has reported recently that there is now a potential significant shortfall in UK electricity generating capacity due to the decommissioning of legacy fossil-fuel and nuclear stations and the continued delays in the provision of viable low-carbon alternatives.
Posted: 16 Dec 2014 | 11:27
In 2013, the DiRAC consortium rolled out the DiRAC driving licence, a software skills aptitude test for researchers wanting to use DiRAC's high-performance computing resources. Now ARCHER, the UK National Supercomputing Service, is to roll out an ARCHER driving test.
Despite their similar names, these tests differ in nature, intent, scale and reward. In this post, EPCC's Mike Jackson, Andrew Turner and Clair Barrass compare and contrast these two supercomputer tests.
Posted: 21 Nov 2014 | 10:29
EPCC's Grand Challenges Optimisation Centre, an Intel Parallel Computing Centre which we announced earlier in the year, has made significant progress over recent months.
The collaboration was created to optimise codes for Intel processors, particularly to port and optimise scientific simulation codes for Intel Xeon Phi co-processors. As EPCC also runs the ARCHER supercomputer, which contains a large number of Intel Xeon processors (although no accelerators or co-processors), for EPSRC and other UK research funding councils, we also have a strong focus on ensuring that scientific simulation codes are highly optimised for these processors. Therefore, the IPCC work at EPCC has been concentrating on improving the performance of a range of codes that are heavily used for computational simulation in the UK on both Intel Xeon and Intel Xeon Phi processors.