Accelerator

Early experiences with KNL

Author: Adrian Jackson
Posted: 29 Jul 2016 | 16:45

Initial experiences on early KNL

Updated 1st August 2016 to add a sentence describing the MPI configurations of the benchmarks run.
Updated 30th August 2016 to add CASTEP performance numbers on Broadwell with some discussion

EPCC was lucky enough to be allowed access to Intel's early KNL (Knights Landing, Intel's new Xeon Phi processor) cluster, through our IPCC project.  KNL Processor Die

KNL is a many-core processor, successor to the KNC, that has up to 72 cores, each of which can run 4 threads, and 16 GB of high bandwidth memory stacked directly on to the chip.

EPCC joins the OpenACC consortium

Author: Adrian Jackson
Posted: 18 Jul 2013 | 14:00

EPCC has recently joined the OpenACC consortium. OpenACC, a directives-based parallel programming standard, is designed to simplify the programming and utilisation of heterogenous computer systems, where standard CPUs and accelerators (such as GPUs) are combined.   Using OpenACC, developers can specify loops and regions of code in standard C, C++ and Fortran to be offloaded from a CPU to an attached accelerator, and also target parallelism on a range of different CPUs and accelerators without having to modify source code.

From multi to many cores: Intel Xeon Phi at EPCC

Author: Iain Bethune
Posted: 12 Apr 2013 | 14:30

Two shiny new Intel Xeon Phi 5110P co-processors have recently arrived at EPCC.

Based on Intel's Many Integrated Core (MIC) architecture, each card comprises 60 cores with 4-way SMT and a 512 bit wide SIMD vector unit.  At a clock speed of 1.053 GHz, this gives an aggregate peak double precision floating point performance of 1.01 TFLOP/s - all in a PCI card package, and using less than 225 Watts of power.  

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