Intel

Advanced systems engineering for cybersecurity

Author: Kostas Kavoussanakis
Posted: 24 Jul 2020 | 16:26

 

EPCC has collaborated with Intel® and Illuminate Technologies to investigate innovative performance-enhancing, packet-processing approaches within the type of Cloud environment expected to be seen in 5G deployments. 

Optimising traffic handling in cloud environments for cyber security

Author: Kostas Kavoussanakis
Posted: 26 Nov 2019 | 13:38

Illuminate Technologies works with EPCC and Intel® on a collaborative project funded by Scottish Enterprise under the CodeOpt Scotland programme to actively seek out innovative performance-enhancing, packet-processing approaches within the type of Cloud environment expected to be seen in 5G deployments.

Collaboration delivers competitive products faster

Author: Kostas Kavoussanakis
Posted: 21 Jun 2019 | 10:32

Optos is a leading provider of medical products and services to eyecare professionals. A collaboration between Optos, EPCC, and Intel has led to significant improvement in the performance of a software algorithm used in a product under development by the company.

The project set out to identify a suitably priced Intel multicore processor on which to run the company’s code, and to accelerate an important Optos machine-learning code. The project baseline was Optos code running on a specific Intel chip and the target was to reduce its runtime to below 12 seconds on the preferred chip.

The Intel Parallel Computing Centre at EPCC

Author: Adrian Jackson
Posted: 15 Jun 2017 | 13:41

We are entering the fourth year of the Intel Parallel Computing Centre (IPCC). This collaboration on code porting and optimisation has focussed on improving the performance of scientific applications on Intel hardware, specifically its Xeon and Xeon Phi processors.  

Codeopt Scotland: optimising software for Scottish industry

Author: George Graham
Posted: 15 Jun 2017 | 10:41

The CodeOpt Scotland programme is designed to increase company competitiveness by optimising the performance of business-critical software.

NEXTGenIO: the next exciting stage begins!

Author: Michele Weiland
Posted: 24 Nov 2016 | 14:32

NEXTGenIO was one of several EC-funded exascale projects that we started work on last year. Here’s what’s been happening since it launched.

MPI performance on KNL

Author: Adrian Jackson
Posted: 30 Aug 2016 | 12:22

Knights Landing MPI performance

Following on from our recent post on early experiences with KNL performance, we have been looking at MPI performance on Intel's latest many-core processor.

MPI ping-pong latency on KNC and IvyBridge
Figure 1

The MPI performance on the first generation of Xeon Phi processor (KNC) was one of the reasons that some of the applications we ported to KNC had poor performance.  Figures 1 and 2 show the latency and bandwidth of an MPI ping-pong benchmark running on a single KNC and on a 2x8-core IvyBridge node.

Early experiences with KNL

Author: Adrian Jackson
Posted: 29 Jul 2016 | 16:45

Initial experiences on early KNL

Updated 1st August 2016 to add a sentence describing the MPI configurations of the benchmarks run.
Updated 30th August 2016 to add CASTEP performance numbers on Broadwell with some discussion

EPCC was lucky enough to be allowed access to Intel's early KNL (Knights Landing, Intel's new Xeon Phi processor) cluster, through our IPCC project.  KNL Processor Die

KNL is a many-core processor, successor to the KNC, that has up to 72 cores, each of which can run 4 threads, and 16 GB of high bandwidth memory stacked directly on to the chip.

Intel compiler on ARCHER

Author: Adrian Jackson
Posted: 26 Apr 2016 | 13:07

Bug

I had a recent query from some users with a problem with the default version of the Intel Fortran compiler on ARCHER (v15.0.2.164).  It was a nice query to get because the users had done all the work already; they'd identified the problem, found a test code that demonstrated it, and told me what the solution would be for them.

Fortunately, the solution was easy, this bug has been fixed in a newer version of the compiler (16.0.2.181), which is installed and available on ARCHER, but just isn't the default (we tend to keep the default version slightly behind the latest release but as new as possible), so they simply have to swap the compiler modules then their code can compile and run correctly.

HPC hardware in 2016 and beyond

Author: Adrian Jackson
Posted: 19 Apr 2016 | 23:14

Anyone taking more than a passing interest in HPC hardware recently will have noticed that there are a number of reasonably significant trends coming to fruition in 2016. Of particular interest to me are on-package memory, integrated functionality, and new processor competitors.  Intel Xeon Phi (KNL) Die

On-package memory, memory that is directly attached to the processor, has been promised for a number of years now. The first product of this type I can remember was Micron's Hybrid Memory Cube around 2010/2011, but it's taken a few years for the hardware to become mature enough (or technically feasible and cheap enough) to make it to mass market chips. We now have it in the form of MCDRAM for Intel's upcoming Xeon Phi processor (Knights Landing), and as HBM2 on Nvidia's recently announced P100 GPU.

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