Adrian Jackson's blog

Does array index order affect performance?

A couple of weeks ago I was teaching an ARCHER Modern Fortran course, and one of the things we discuss during the course is index ordering for multi-dimension arrays.  This course is an introduction to modern Fortran (primarily F90/F95), so we don't go into lots of details about parallel or performance programming, but as attendees are likely to be using Fortran for computational simulation it is important they understand which array dimensions are contiguous in memory so that they don't accidentally write code that is much slower than it should be.

Figure 1: Performance using the GNU compiler

During one of the practical sessions on the course, one of the students wrote a little program to investigate the performance impact of iterating through array elements in a non-contiguous order.  They also included some code to investigate if there is a performance impact when using allocatable array rather than static arrays (I'd mentioned it shouldn't impact performance but I obviously wasn't convincing enough...).

Or why debugging is hard and parallel debugging doubly so

Debugging programs is hard. I give a lecture on debugging for the Programming Skills module of EPCC's MScs in HPC and HPC with Data Science where we try to point out common programming mistakes, programming strategies for making bugs less likely, and the skills and tools required for investigating, identifying, and fixing bugs.

Lancaster University, 7-8 April 2016

The programme for the HPC-CORE (High Performance Computing-based Computational fluid dynamics for Offshore Renewable Energy) workshop has now been published. This event brings together scientific specialists from Engineering, Atmospheric and Environmental Sciences, and HPC experts to discuss the state of the art for simulation software, and the leading-edge simulations being undertaken with such software.

EPCC at SC15

Preparations for EPCC's booth at SC15 are currently in full swing. This year we have revamped our stand, ordering a custom-built display (see pics below). 

In previous years we have used a combination of smaller displays to populate the space we have at the conference. However, it's often hard to get a coherent and consistent look for the booth when using an adhoc approach like this, hence this years' decision to create a display that is tailored to the space we have on the exhibition floor at Supercomputing.

It's not often that the internecine rivalries of the HPC research and development community spill over into the public arena. However, a video recently posted on YouTube (and the associated comments), ostensibly a light-hearted advert for a SC15 tutorial on heterogenous programming, shows how real and deep these rivalries can be.

Big Data vs HPC

Whilst I was writing my talk for last week's How to Make Big Data work for your business seminar at Edinburgh BioQuarter, it occurred to me that the way computational simulation codes have evolved over the last 40 years has really been a response to big data issues. 

The LINPACK library (often known as HPL) has been used to benchmark large-scale computers for over 20 years, with the results being published in the Top500 list. But does it accurately reflect the performance of real applications?

ParCo Symposium

Experiences of porting and optimising code for Xeon Phi processors

EPCC is jointly organising a symposium at the ParCo conference on experiences from those working on porting and optimising codes for this architecture about the challenges and successes they have experienced when working with the Xeon Phi, and how these also apply to standard parallel computing hardware.

Discussions on computing

Myself and Fiona Reid recently presented a 2-day course on porting and optimising for the Xeon Phi at the NGCM (Next Generation Computational Modelling) summer academy in Southampton. 

This one-week academy is designed to give PhD students some of the skills they need to undertake the range of computational simulations and data analysis tasks that their work requires.

The final analysis and future plans

A week ago we finished our 5 days of intensive work optimising CP2K (and to a lesser extent GS2) for Xeon Phi processors. As discussed in previous blog posts (Day4, Day3, Day2, Day1), this was done in conjunction with research engineers from Colfax, and built on the previous year's work on these codes by EPCC staff through the Intel-funded IPCC project.