ParCo 2015 Symposium on Experiences of porting and optimising code for Xeon Phi processors

The flop-to-watt performance potentially available from Intel’s Xeon Phi co-processor makes it very attractive for computational simulation. With its full x86 instruction set, cache-coherent architecture, and support for MPI and OpenMP parallelisations, it is in theory relatively straight forward to port applications to the platform.  However, a number of factors can make it difficult to obtain good performance for many codes, including: the relatively high core count, the low clock speed of the cores, the in-order instruction restrictions, 512-bit wide vector units, and low memory per core.

This mini-symposium, organised by the Intel Parallel Computing Centres at EPCC and the University of Bristol, provides a forum for those working on porting and optimising codes for this architecture to present the challenges and successes they have experienced when working with the Xeon Phi, and how these also apply to standard parallel computing hardware.

Symposium Schedule

The symposium schedule is in this document.  We thanks those who submitted abstracts for the symposium and provided the content to make this a great schedule.  See you all on the 1st of September for what looks like a very interesting meeting!

How to Participate

We seek contributions in the form of 1-page abstracts. Topics of interest include, but are not restricted to:

  • Experiences, both positive and negative, of optimising simulation codes on Xeon Phi
  • Algorithms and algorithmic changes required to exploit highly concurrent devices and wide vector units
  • Experiences of the different modes of programming the Xeon Phi, and of parallelising across multiple Xeon Phi’s within and across nodes.
  • Models and tools to enable understanding and performance prediction on highly parallel hardware
  • Memory management techniques for applications on low-memory per thread/core devices
  • Application experience and performance on highly parallel architectures, including performance and flop-to-watt comparison with CPUs and GPUs

Please send your abstracts to parco-xeon-phi@mlist.is.ed.ac.uk by the 24th July 2015 (note extended deadline). Your contributions will be reviewed by the mini-symposium organisers and you will be notified of acceptance as soon as possible thereafter.

Important Dates

  • Abstract submission deadline:     24th July 2015    
  • Acceptance notification:               28th July 2015
  • Early Bird Registration Deadline:  31st July 2015
  • Conference:                                 1st – 4th September 2015
  • Mini-symposium:                          1st September 2015

Organisers

  • Adrian Jackson, EPCC
  • Simon McIntosh-Smith, University of Bristol
  • Michèle Weiland, EPCC
  • Mark Parsons, EPCC

More Information

Please see the ParCo website for registration details and more information on the conference.

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