From multi to many cores: Intel Xeon Phi at EPCC

Author: Iain Bethune
Posted: 12 Apr 2013 | 14:30

Two shiny new Intel Xeon Phi 5110P co-processors have recently arrived at EPCC.

Based on Intel's Many Integrated Core (MIC) architecture, each card comprises 60 cores with 4-way SMT and a 512 bit wide SIMD vector unit.  At a clock speed of 1.053 GHz, this gives an aggregate peak double precision floating point performance of 1.01 TFLOP/s - all in a PCI card package, and using less than 225 Watts of power.  

Only 10 years ago, the National Service HPCx Phase 1 delivered 2.2 TFLOP/s peak, occupied over 40 cabinets and was the sole capability computing resource for the entire UK computational science community.  It seems to have come a long way in 10 years!

The Xeon Phi cards will shortly be installed as part of EPCC's internal cluster 'Hydra' and made available to staff and students for testing and evaluation of HPC applications. Early candidate applications include CP2K (ab initio molecular dynamics), TPLS (multi-phase fluid dynamics), ACTA (genetics) and Ludwig (lattice Boltzmann).