FPGAs for HPC, but this time it’s different
Posted: 10 Aug 2021 | 10:05
For over a decade our community has enjoyed significant performance benefits by leveraging heterogeneous supercomputers. Whilst GPUs are the most common form of accelerator there are also other hardware technologies which can be complementary.
Field Programmable Gate Arrays (FPGAs) enable developers to directly configure the chip, effectively enabling their application to run at the electronics level. There are potential performance and power benefits to tailoring code execution and avoiding the general purpose architecture imposed by CPUs and GPUs, and as such FPGAs have been popular in embedded computing for many years but have not yet enjoyed any level of uptake in HPC.
There have been several efforts over the years to make FPGAs more mainstream, however factors such as reliance on esoteric programming technologies proved to be barriers to entry. But in the last few years there have been some very interesting developments. Vendors have significantly advanced the hardware offering, providing larger, more capable chips, with some very exciting next-generation FPGAs to be released later in 2021. They have also invested heavily in the software ecosystem, with much improved programming environments and documentation. As shrinkages in CPU process size and the associated performance benefits are slowing significantly, it is worth reviewing how FPGAs can help accelerate HPC computational kernels.
To this end, the ExCALIBUR Hardware and Enabling Software (H&ES) programme has awarded us funding for an FPGA testbed. H&ES addresses the challenges and opportunities offered by computing at the exascale, and is looking to invest in novel hardware testbed systems upon which UK scientific software developers can explore their codes.
EPCC’s FPGA testbed will be run in collaboration with University College London and the University of Warwick, and will be physically located in Edinburgh. It will represent a complete ecosystem for FPGA programming: in addition to the hardware itself, all required libraries and licences will be pre-installed, and all the building and emulation nodes, training, and full documentation will be provided. There is also associated effort to develop an enabling software ecosystem, further lowering the barrier to entry for application developers, for instance integrating existing FPGA tools and libraries and developing new ones to support users.
We are currently in the process of installing the hardware, and in addition to the current generation FPGAs we are excited to have been chosen to host Xilinx’s next-generation Versal ACAP architecture later in the year.
Nick Brown, EPCC