Posted: 3 Jun 2016 | 16:09
It's a good time to take stock of our achievements and reflect on how to focus our efforts in the final phase. Also to consider life after the project ends: how do we want to exploit the technologies we have developed and the knowledge we have gained? How do we ensure a lasting legacy for Adept?
Posted: 27 May 2016 | 10:15
The NEXTGenIO project represents a step along the Exascale pathway.
We are developing a prototype platform that utilises the latest developments in memory technology, and that will offer vastly improved I/O performance compared to current HPC machines. The system will be developed end-to-end by the project partners – from inception through to delivery, with a full suite of systemware that can make use of the new technologies.
Posted: 5 May 2016 | 16:43
Recently I seem to have had many conversations about programming languages for HPC. In some ways this is not a new subject - I have been having similar conversations for the last 20 years. However as HPC hardware evolves, machines become more complex and the issues that need to be addressed by programmers also become more complex. So it is not surprising that we are wondering if there is more the compiler could be doing to help us.
Posted: 19 Apr 2016 | 23:14
Anyone taking more than a passing interest in HPC hardware recently will have noticed that there are a number of reasonably significant trends coming to fruition in 2016. Of particular interest to me are on-package memory, integrated functionality, and new processor competitors.
On-package memory, memory that is directly attached to the processor, has been promised for a number of years now. The first product of this type I can remember was Micron's Hybrid Memory Cube around 2010/2011, but it's taken a few years for the hardware to become mature enough (or technically feasible and cheap enough) to make it to mass market chips. We now have it in the form of MCDRAM for Intel's upcoming Xeon Phi processor (Knights Landing), and as HBM2 on Nvidia's recently announced P100 GPU.
Posted: 30 Mar 2016 | 17:46
Does array index order affect performance?
A couple of weeks ago I was teaching an ARCHER Modern Fortran course, and one of the things we discuss during the course is index ordering for multi-dimension arrays. This course is an introduction to modern Fortran (primarily F90/F95), so we don't go into lots of details about parallel or performance programming, but as attendees are likely to be using Fortran for computational simulation it is important they understand which array dimensions are contiguous in memory so that they don't accidentally write code that is much slower than it should be.
Figure 1: Performance using the GNU compiler
During one of the practical sessions on the course, one of the students wrote a little program to investigate the performance impact of iterating through array elements in a non-contiguous order. They also included some code to investigate if there is a performance impact when using allocatable array rather than static arrays (I'd mentioned it shouldn't impact performance but I obviously wasn't convincing enough...).
Posted: 30 Mar 2016 | 17:23
This blog article comes from one of our current Phd students: Athina Frantzana, who is researching the obstacles facing women in the HPC community, and how equality can be improved.
The under-representation of women in STEM workforces has been a widely discussed subject in recent years. However, the recording and analysis of data regarding the gender balance of HPC remains rare.
Our study is a preliminary analysis of workforce and research participation in HPC, and aims to quantify the current level of representation of women in HPC and to provide a baseline for evaluating possible reasons and suggesting ways for future changes to the demographics.
Posted: 24 Feb 2016 | 16:41
Or why debugging is hard and parallel debugging doubly so
Debugging programs is hard. I give a lecture on debugging for the Programming Skills module of EPCC's MScs in HPC and HPC with Data Science where we try to point out common programming mistakes, programming strategies for making bugs less likely, and the skills and tools required for investigating, identifying, and fixing bugs.
Posted: 31 Jan 2016 | 23:07
Lancaster University, 7-8 April 2016
The programme for the HPC-CORE (High Performance Computing-based Computational fluid dynamics for Offshore Renewable Energy) workshop has now been published. This event brings together scientific specialists from Engineering, Atmospheric and Environmental Sciences, and HPC experts to discuss the state of the art for simulation software, and the leading-edge simulations being undertaken with such software.
Posted: 20 Nov 2015 | 15:15
Posted: 12 Nov 2015 | 13:49
A recent MSc project at EPCC has paved the way for improved diagnosis of eye-related conditions.