Posted: 19 Apr 2016 | 23:14
Anyone taking more than a passing interest in HPC hardware recently will have noticed that there are a number of reasonably significant trends coming to fruition in 2016. Of particular interest to me are on-package memory, integrated functionality, and new processor competitors.
On-package memory, memory that is directly attached to the processor, has been promised for a number of years now. The first product of this type I can remember was Micron's Hybrid Memory Cube around 2010/2011, but it's taken a few years for the hardware to become mature enough (or technically feasible and cheap enough) to make it to mass market chips. We now have it in the form of MCDRAM for Intel's upcoming Xeon Phi processor (Knights Landing), and as HBM2 on Nvidia's recently announced P100 GPU.
Posted: 14 Apr 2016 | 21:02
Writing programs assuming that they will be incorrect
I was thinking about development methodologies and software design principles recently and have decided that one of the things I've learned is that it is essential to write programs with the assumption they are going to fail.
I don't think that any of us like to think that the programs we write or maintain will go wrong, or have mistakes/problems in them. However, as I've discussed previously, it is very hard to develop code without making mistakes: coding mistakes, algorithmic errors, mistaken assumptions, etc...
Posted: 13 Apr 2016 | 14:47
SHAPE (SME HPC Adoption Programme in Europe) is a pan-European initiative supported by PRACE (Partnership for Advanced Computing in Europe). The Programme aims to raise awareness and provide European SMEs with the expertise necessary to take advantage of the innovation possibilities created by high-performance computing (HPC), thus increasing their competitiveness. SHAPE allows SMEs to benefit from the expertise and knowledge developed within the top-class PRACE Research Infrastructure.
Posted: 7 Apr 2016 | 16:36
I have become a bit of a fan of the distributed revision control provided by git. In my day-to-day work at EPCC, I find myself developing and running code across multiple machines. Trying to keep a code base coherent across all these systems would be a bit of a nightmare were it not for git or any other source control revision system. Arguably, SVN would work as well but I somewhat lost my faith in SVN after trying to commit files over a slow and unstable connection while travelling on a train.
Posted: 5 Apr 2016 | 12:30
It was not without a certain element of trepidation that I volunteered to help out at our offering at this year's Edinburgh International Science Festival: Junkyard Clusters.
The activity basically involved taking a stripped down Dell desktop system and, in a workshop format, with a host of mostly young participants, walking them through putting the machine back together, networking the systems up and from the now working systems getting them to collaboratively build a fractal image.
Posted: 31 Mar 2016 | 09:30
The Software Sustainability Institute's Collaborations Workshop 2016 is now over. If you blinked, you missed it. You shall now have to wait until 27-29th March 2017 for the next one, to be held at the Leeds Business School. I still think that this is one of the best networking conferences around and well worth attending, though for the purposes of full disclosure I have to admit that I have a dual role: as a peripheral organiser as well as a full workshop attendee. The workshop runs over two days and is followed by a hack day which I was unable to attend because of other commitments.
Posted: 30 Mar 2016 | 17:46
Does array index order affect performance?
A couple of weeks ago I was teaching an ARCHER Modern Fortran course, and one of the things we discuss during the course is index ordering for multi-dimension arrays. This course is an introduction to modern Fortran (primarily F90/F95), so we don't go into lots of details about parallel or performance programming, but as attendees are likely to be using Fortran for computational simulation it is important they understand which array dimensions are contiguous in memory so that they don't accidentally write code that is much slower than it should be.
Figure 1: Performance using the GNU compiler
During one of the practical sessions on the course, one of the students wrote a little program to investigate the performance impact of iterating through array elements in a non-contiguous order. They also included some code to investigate if there is a performance impact when using allocatable array rather than static arrays (I'd mentioned it shouldn't impact performance but I obviously wasn't convincing enough...).
Posted: 30 Mar 2016 | 17:23
This blog article comes from one of our current Phd students: Athina Frantzana, who is researching the obstacles facing women in the HPC community, and how equality can be improved.
The under-representation of women in STEM workforces has been a widely discussed subject in recent years. However, the recording and analysis of data regarding the gender balance of HPC remains rare.
Our study is a preliminary analysis of workforce and research participation in HPC, and aims to quantify the current level of representation of women in HPC and to provide a baseline for evaluating possible reasons and suggesting ways for future changes to the demographics.
Posted: 21 Mar 2016 | 10:13
EPCC staff have enthusiastically engaged with the ‘Love to Ride, Edinburgh’ cycling challenge. This is an effort to get more people to cycle within Edinburgh for environmental and health reasons through fun workplace competitions. Workplaces compete in a league based on the number of staff and EPCC is currently topping the departmental league (50-199 staff) .
Posted: 20 Mar 2016 | 10:01
Broadening participation in HPC: taking outreach to the next level
One of the reasons why EPCC set up Women in HPC is because we recognised there was a problem. The problem was the apparent lack of women in the supercomputing community. When my colleagues and I started Women in HPC, our purpose was very clear: to recruit and retain women in the international HPC workforce.