RISC-V Summit Europe

RISC-V is an open source, modular, Instruction Set Architecture (ISA), which is the blueprint used by software to drive the central processing unit (CPU). This open and modular nature means it is easy to "pick and mix" various parts of the standard to design open, or closed, CPU implementations, and we are already seeing many designs based upon RISC-V. 

The technology is growing extremely quickly, with over 3000 members (including some of the world’s largest technology companies) across more than 70 countries, and 10 billion RISC-V cores already manufactured. 

ExCALIBUR RISC-V testbed

In EPCC we host a RISC-V testbed as part of the ExCALIBUR Hardware and Enabling Software Programme, with the objective being to give high performance computing (HPC) and machine learning (ML) developers free access to the technology so they can experiment with it for their workloads. At the RISC-V Summit in Barcelona in June I presented a poster describing the lessons learned from the RISC-V testbed, what worked well and the challenges we faced, as well as the priority areas to be  addressed by the community to make the technology more attractive to HPC users.

RISC-V Summit Europe

The summit started with a half day focussing on the RISC-V Special Interest Groups (SIGs). These dedicated groups have been set up to address the requirements and developments of key areas, and it was a good opportunity not only to participate in the SIGs in which I am already involved, but also to gain a wider appreciation of activity across the community.

The main part of the summit started the next day and was a mixture of presentations, posters, and networking. In addition to the technical programme, the summit was also a great opportunity to meet many of the people and companies who are enthusiastic about RISC-V and driving forwards key parts of the ecosystem. It was fascinating to hear what people are up to. Especially interesting to me were some of the talks by people in industrial sectors ranging from automotive to space exploration who see RISC-V as an important future technology to integrate with their products and solutions.

The summit strengthened my conviction that RISC-V has an extremely bright future, and that in HPC we currently have a unique opportunity to influence the standard and roadmap to produce technologies that are highly suited to our workloads. 

There are a large number of very exciting developments in progress across the RISC-V ecosystem. If you are interested in RISC-V and wish to experiment with the technology, then visit the ExCALIBUR RISC-V testbed website to read about accessing the system.

Links

ExCALIBUR H&ES RISC-V testbed

RISC-V Summit Europe