Dr Nick Brown

Senior Research Fellow
+44 (0) 131 650 6420

I am interested in the role that novel hardware can play in future supercomputers, and am specifically motivated by the grand-challenge of how we can ensure scientific programmers are able to effectively exploit such technologies without extensive hardware/architecture expertise. My research combines novel algorithmic techniques for this new hardware, programming language & library design, and compilers. I coordinate knowledge exchange for the ExCALIBUR exascale software programme, and chair the RISC-V International HPC SIG. I head up EPCC's PhD programme and am course organiser for the in-person and online Parallel Design Patterns MSc modules.

I am currently undertaking a Royal Society of Edinburgh personal research fellowship.

Nick Brown

About my research

From FPGAs, to AI engines, to RISC-V, to CGRAs, we are awash with novel hardware that has the potential to play an important role in future supercomputers. Moreover, many of these are highly energy efficient and-so as the community looks towards greener supercomputing these have an important potential role to play in moving towards Net Zero.

However, many of these technologies are very different from the traditional CPUs and GPUs that are currently ubiquitous in HPC and require the development of new techniques in order to exploit them most effectively. I have over 80 peer reviewed publications largely centred around the following: 

  • Driven by specific kernels and applications, developing algorithmic techniques for novel hardware. For instance, understanding the most appropriate ways in which we can restructure Von-Neumann based CPU/GPU algorithms into a dataflow style for FPGAs and CGRAs.
  • New programming constructs and paradigms for novel hardware that then feed into libraries and tools such as Domain Specific Languages (DSLs).
  • Compiler techniques to enable automatic transformation and optimisation in supporting codes running on a variety of novel architectures, ideally with minimal or no input required from the programmer.

I am PI of the EPSRC ExCALIBUR H&ES RISC-V testbed and CGRA testbeds, and am chair of the RISC-V International HPC SIG leading the organisation of the RISC-V for HPC workshop series at ISC and SC. I am a Co-I on the ExCALIBUR xDSL cross cutting project. I was also a Co-I on the ExCALIBUR H&ES FPGA testbed. I also coordinate knowledge exchange for the ExCALIBUR exascale software programme.

Previously, I led the interactive supercomputing work-package on the VESTEC H2020 EU project which was researching fusing real-time data and HPC for urgent computing workloads and as part of this led the organisation of the UrgentHPC initiative which involved workshops at SC19, SC20, SC21, SC22, and ISC23. I was PI of a collaboration with Rock Solid Imaging (RSI) where we explored the role of machine learning for optimising petrophysical interpretation of well log data, ultimately reducing the time per well down to a couple of days. I have worked extensively with the Met Office developing their main high-resolution atmospheric model called MONC, and have also worked with the British Geological Survey modernising their geomagnetic model to take advance of modern supercomputers, both of these codes run daily in production on latest generation supercomputers.

You can find more about me, as well as my list of publications, on my personal webpage at https://nickbrown.online

PhD student opportunities

I am always open to supervising PhD students, if you are interested in my research topics then get in touch!

Current PhD students
  • Mark Klaisoongnoen who is researching the role of FPGAs and AIEs in accelerating quantitative finance workloads
  • Gabriel Rodríguez Canal who is exploring solving some of the programming challenges associated with running HPC codes on FPGAs
  • David Kacs whose topic is to explore automatic optimisation of codes for the Cerebras CS-2
Graduated PhD students
  • Ludovic Capelli (graduated 2023) who developed novel vertex centric graph processing techniques to enable the use of HPC to provide a step change in capability. This research culminated in Ludovic setting a world record in terms of the largest graph that could be processed in a single shared memory node.
  • Maurice Jamieson (graduated 2022) who researched novel compiler techniques to enable the execution of Python code on extremely energy and memory constrained devices. Democratising the use of these complex embedded devices, Maurice's research enabled codes of unlimited size to process data-sets of arbitrary length within around 6KB of memory.


I head up EPCC's PhD programme and am a course organiser for the Parallel Design Patterns module on both the in-person and online EPCC's MSc in High Performance Computing programmes. I also lecture on several other courses too throughout the year and have supervised over 25 MSc dissertation students. I also hosted PRACE Summer of HPC students over six consecutive summers between 2013 and 2019, with these students typically working on developing and enhancing EPCC's outreach activities.