Preview: RISC-V at HPC Asia

24 January 2024

HPC Asia, which will run from 25–27 January in Nagoya, Japan, is an opportunity for EPCC to further engage with some of the very exciting activities that are happening around HPC in this part of the world.

The International Conference on High Performance Computing in the Asia-Pacific Region, known as HPC Asia, is an international conference series that covers HPC technologies, fostering the exchange of ideas, research results, and case studies related to all issues of high performance computing. 


As part of the RISC-V ExCALIBUR H&ES testbed I have been involved in organising several workshops on RISC-V for HPC at ISC and SC in collaboration with the RISC-V HPC Special Interest Group (SIG). These have been extremely well received and fostered significant discussion and interest from the audience. RISC-V is an open, modular, and community-driven Instruction Set Architecture (ISA) with vendors then providing hardware implementations built upon it for CPUs, GPUs, and other accelerators. Indeed, Qualcomm announced late last year that they have shipped over a billion RISC-V powered devices, and the technology is expanding very quickly.

The HPC SIG supports the increased use of RISC-V in HPC, and as part of this we are running a workshop on RISC-V for HPC  at HPC Asia. The organisation of the workshop this time is led by Michael Wong from Codeplay, with myself and John Davis (who leads the HPC SIG) also helping to organise the session, and we have a busy morning workshop scheduled. Whilst there will be numerous talks from RISC-V researchers and vendors who are based in the Asia Pacific region, I will also be talking about our own RISC-V testbed and offering access to it to encourage people to experiment with the technology for their workloads.

It promises to be a busy and interesting time ahead at the conference, in addition to the RISC-V workshop itself. In my role leading knowledge exchange for the ExCALIBUR UK exascale software programme, I am looking forward to hearing about some of the other activities happening around HPC in this part of the world, and how UK projects might leverage and connect more closely with some of them.  


HPC Asia:

Third International workshop on RISC-V for HPC at HPC Asia:

Fourth International workshop on RISC-V for HPC at ISC24:

Second International workshop on RISC-V for HPC at SC23:

ExCALIBUR UK exascale software programme:



Dr Nick Brown
Nick Brown