FPGA testbed

The Field Programmable Gate Array (FPGA) testbed provides access to a variety of reconfigurable computing technologies.

Testbed image


# Nodes
4 compute nodes


  • AMD Xilinx Alveo U280 with 1 million LUTs, 8GB HBM2 and 32GB DDR-DRAM. 
  • AMD Xilinx Alveo U250 with 1.3 million LUTs, 64GB DDR-DRAM
  • AMD Xilinx VCK5000 with Versal FPGA containing 400 AI-engines and on-board 32GB DDR-DRAM 
  • Alpha Data ADM PA-100 which provides Versal FPGA containing 400 AI-engines
  • Bittware 520N-MX, containing Intel Stratix-10 FPGA and 16GB HBM2

Storage technologies and specs
Access to the NEXTGenIO system which has a 217TB lustre file system.

Interconnect technologies and specs
Dual-rail Intel Omnipath at 100 Gbit/s between the nodes.

QSFP28 100Gbit/s direct connection between the FPGA cards via QSFP28 router.

Layout/Physical system scale
The system is housed in the NextGenIO racks.

Cooling tech and specs
The system is composed of 4 air-cooled servers, housed in air-cooled racks.

Scheduler details

System OS Details
CentOS 7

Science and applications

The FPGA testbed is funded by ExCALIBUR H&ES programme and intended to give HPC code developers access to a variety of FPGA technologies that they can use to experiment accelerating their codes. Some examples of successes:


If you are interested in using the FPGA testbed prototype for your research, please see https://fpga.epcc.ed.ac.uk/ for details of how to gain access.


The FPGA testbed system is managed by Adrian Jackson and Nick Brown at EPCC.